Messages in this thread Patch in this message | | | From | Nick Forrington <> | Subject | [PATCH 07/20] perf vendors events arm64: Arm Cortex-A32 | Date | Tue, 10 May 2022 11:47:45 +0100 |
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Add PMU events for Arm Cortex-A32 Update mapfile.csv
Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a32.json
which is based on PMU event descriptions from the Arm Cortex-A32 Technical Reference Manual.
Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json
which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs.
Signed-off-by: Nick Forrington <nick.forrington@arm.com> --- .../arch/arm64/arm/cortex-a32/branch.json | 11 +++++++ .../arch/arm64/arm/cortex-a32/bus.json | 17 ++++++++++ .../arch/arm64/arm/cortex-a32/cache.json | 32 +++++++++++++++++++ .../arch/arm64/arm/cortex-a32/exception.json | 14 ++++++++ .../arm64/arm/cortex-a32/instruction.json | 29 +++++++++++++++++ .../arch/arm64/arm/cortex-a32/memory.json | 8 +++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 7 files changed, 112 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json new file mode 100644 index 000000000000..7c018f439206 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index c24291e0d757..ef3af958aae5 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -18,6 +18,7 @@ 0x00000000410fc090,v1,arm/cortex-a9,core 0x00000000410fc0e0,v1,arm/cortex-a17,core 0x00000000410fc0f0,v1,arm/cortex-a15,core +0x00000000410fd010,v1,arm/cortex-a32,core 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core -- 2.25.1
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