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Subject[PATCH 06/20] perf vendors events arm64: Arm Cortex-A17
Date
Add PMU events for Arm Cortex-A17
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a17.json

which is based on PMU event descriptions from the Arm Cortex-A17 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <nick.forrington@arm.com>
---
.../arch/arm64/arm/cortex-a17/branch.json | 17 ++++++
.../arch/arm64/arm/cortex-a17/bus.json | 26 +++++++++
.../arch/arm64/arm/cortex-a17/cache.json | 53 ++++++++++++++++++
.../arch/arm64/arm/cortex-a17/exception.json | 11 ++++
.../arm64/arm/cortex-a17/instruction.json | 56 +++++++++++++++++++
.../arch/arm64/arm/cortex-a17/memory.json | 20 +++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
7 files changed, 184 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
new file mode 100644
index 000000000000..2f2d137f5f55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
new file mode 100644
index 000000000000..4978c84a48e1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
@@ -0,0 +1,26 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
new file mode 100644
index 000000000000..f36a2669c2b6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
@@ -0,0 +1,53 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
new file mode 100644
index 000000000000..5a4e23ce0bd0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
@@ -0,0 +1,11 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF"
+ },
+ {
+ "ArchStdEvent": "EXC_HVC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
new file mode 100644
index 000000000000..62aa70e207c0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
@@ -0,0 +1,56 @@
+[
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
new file mode 100644
index 000000000000..e3d08f1f7c92
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
@@ -0,0 +1,20 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 536652b8580b..c24291e0d757 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -16,6 +16,7 @@
0x00000000410fc070,v1,arm/cortex-a7,core
0x00000000410fc080,v1,arm/cortex-a8,core
0x00000000410fc090,v1,arm/cortex-a9,core
+0x00000000410fc0e0,v1,arm/cortex-a17,core
0x00000000410fc0f0,v1,arm/cortex-a15,core
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
--
2.25.1
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