Messages in this thread | | | Date | Wed, 18 May 2022 13:58:23 +0100 | Subject | Re: [PATCH 06/20] perf vendors events arm64: Arm Cortex-A17 | From | Robin Murphy <> |
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On 2022-05-10 11:47, Nick Forrington wrote: > Add PMU events for Arm Cortex-A17 > Update mapfile.csv > > Event data based on: > https://github.com/ARM-software/data/tree/master/pmu/cortex-a17.json > > which is based on PMU event descriptions from the Arm Cortex-A17 Technical > Reference Manual. > > Mapping data (for mapfile.csv) based on: > https://github.com/ARM-software/data/blob/master/cpus.json > > which is based on Main ID Register (MIDR) information found in the Arm > Technical Reference Manuals for individual CPUs. > > Signed-off-by: Nick Forrington <nick.forrington@arm.com> > --- [...] > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index 536652b8580b..c24291e0d757 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -16,6 +16,7 @@ > 0x00000000410fc070,v1,arm/cortex-a7,core > 0x00000000410fc080,v1,arm/cortex-a8,core > 0x00000000410fc090,v1,arm/cortex-a9,core > +0x00000000410fc0e0,v1,arm/cortex-a17,core > 0x00000000410fc0f0,v1,arm/cortex-a15,core > 0x00000000410fd030,v1,arm/cortex-a53,core > 0x00000000420f1000,v1,arm/cortex-a53,core
Note that 0x410fc0d0 is also Cortex-A17. Those are found in at least Rockchip's RK3288 SoCs, which are still quite widely used.
Robin.
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