Messages in this thread Patch in this message | | | From | Nick Forrington <> | Subject | [PATCH 03/20] perf vendors events arm64: Arm Cortex-A8 | Date | Tue, 10 May 2022 11:47:41 +0100 |
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Add PMU events for Arm Cortex-A8 Update mapfile.csv
Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a8.json
which is based on PMU event descriptions from the Arm Cortex-A8 Technical Reference Manual.
Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json
which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs.
Signed-off-by: Nick Forrington <nick.forrington@arm.com> --- .../arch/arm64/arm/cortex-a8/branch.json | 8 ++ .../arch/arm64/arm/cortex-a8/cache.json | 77 +++++++++++++++++++ .../arch/arm64/arm/cortex-a8/exception.json | 5 ++ .../arch/arm64/arm/cortex-a8/instruction.json | 38 +++++++++ .../arch/arm64/arm/cortex-a8/memory.json | 5 ++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 6 files changed, 134 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json new file mode 100644 index 000000000000..79f2016c53b0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json new file mode 100644 index 000000000000..a5d70071be57 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json @@ -0,0 +1,77 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json new file mode 100644 index 000000000000..44a3e9f37bd6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json new file mode 100644 index 000000000000..39db07e827d0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json @@ -0,0 +1,38 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json new file mode 100644 index 000000000000..7fea14ff35f3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 9d8ebe3ea6d2..436184ce1ef7 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,6 +14,7 @@ #Family-model,Version,Filename,EventType 0x00000000410fc050,v1,arm/cortex-a5,core 0x00000000410fc070,v1,arm/cortex-a7,core +0x00000000410fc080,v1,arm/cortex-a8,core 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core -- 2.25.1
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