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Subject[PATCH 04/20] perf vendors events arm64: Arm Cortex-A9
Date
Add PMU events for Arm Cortex-A9
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a9.json

which is based on PMU event descriptions from the Arm Cortex-A9 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <nick.forrington@arm.com>
---
.../arch/arm64/arm/cortex-a9/branch.json | 8 +++++
.../arch/arm64/arm/cortex-a9/cache.json | 17 +++++++++++
.../arch/arm64/arm/cortex-a9/exception.json | 5 ++++
.../arch/arm64/arm/cortex-a9/instruction.json | 29 +++++++++++++++++++
.../arch/arm64/arm/cortex-a9/memory.json | 5 ++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
6 files changed, 65 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
new file mode 100644
index 000000000000..79f2016c53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
new file mode 100644
index 000000000000..2149f015193c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
new file mode 100644
index 000000000000..44a3e9f37bd6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
@@ -0,0 +1,5 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
new file mode 100644
index 000000000000..7c018f439206
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
@@ -0,0 +1,29 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "LD_RETIRED"
+ },
+ {
+ "ArchStdEvent": "ST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_RETIRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
new file mode 100644
index 000000000000..7fea14ff35f3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
@@ -0,0 +1,5 @@
+[
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_RETIRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 436184ce1ef7..80f37f8f650b 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -15,6 +15,7 @@
0x00000000410fc050,v1,arm/cortex-a5,core
0x00000000410fc070,v1,arm/cortex-a7,core
0x00000000410fc080,v1,arm/cortex-a8,core
+0x00000000410fc090,v1,arm/cortex-a9,core
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000410fd070,v1,arm/cortex-a57-a72,core
--
2.25.1
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