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    Subject[PATCH 16/20] perf vendors events arm64: Arm Cortex-A78
    Date
    Add PMU events for Arm Cortex-A78
    Update mapfile.csv

    Event data based on:
    https://github.com/ARM-software/data/tree/master/pmu/cortex-a78.json

    which is based on PMU event descriptions from the Arm Cortex-A78 Technical
    Reference Manual.

    Mapping data (for mapfile.csv) based on:
    https://github.com/ARM-software/data/blob/master/cpus.json

    which is based on Main ID Register (MIDR) information found in the Arm
    Technical Reference Manuals for individual CPUs.

    Signed-off-by: Nick Forrington <nick.forrington@arm.com>
    ---
    .../arch/arm64/arm/cortex-a78/branch.json | 17 ++
    .../arch/arm64/arm/cortex-a78/bus.json | 20 +++
    .../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++++++++
    .../arch/arm64/arm/cortex-a78/exception.json | 47 ++++++
    .../arm64/arm/cortex-a78/instruction.json | 80 +++++++++
    .../arch/arm64/arm/cortex-a78/memory.json | 23 +++
    .../arch/arm64/arm/cortex-a78/pipeline.json | 23 +++
    tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
    8 files changed, 366 insertions(+)
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
    create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json

    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
    new file mode 100644
    index 000000000000..2f2d137f5f55
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
    @@ -0,0 +1,17 @@
    +[
    + {
    + "ArchStdEvent": "BR_MIS_PRED"
    + },
    + {
    + "ArchStdEvent": "BR_PRED"
    + },
    + {
    + "ArchStdEvent": "BR_IMMED_SPEC"
    + },
    + {
    + "ArchStdEvent": "BR_RETURN_SPEC"
    + },
    + {
    + "ArchStdEvent": "BR_INDIRECT_SPEC"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
    new file mode 100644
    index 000000000000..579c1c993d17
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
    @@ -0,0 +1,20 @@
    +[
    + {
    + "ArchStdEvent": "CPU_CYCLES"
    + },
    + {
    + "ArchStdEvent": "BUS_ACCESS"
    + },
    + {
    + "ArchStdEvent": "BUS_CYCLES"
    + },
    + {
    + "ArchStdEvent": "BUS_ACCESS_RD"
    + },
    + {
    + "ArchStdEvent": "BUS_ACCESS_WR"
    + },
    + {
    + "ArchStdEvent": "CNT_CYCLES"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
    new file mode 100644
    index 000000000000..0141f749bff3
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
    @@ -0,0 +1,155 @@
    +[
    + {
    + "ArchStdEvent": "L1I_CACHE_REFILL"
    + },
    + {
    + "ArchStdEvent": "L1I_TLB_REFILL"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_REFILL"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB_REFILL"
    + },
    + {
    + "ArchStdEvent": "L1I_CACHE"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_WB"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_REFILL"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_WB"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_ALLOCATE"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB"
    + },
    + {
    + "ArchStdEvent": "L1I_TLB"
    + },
    + {
    + "ArchStdEvent": "L3D_CACHE_ALLOCATE"
    + },
    + {
    + "ArchStdEvent": "L3D_CACHE_REFILL"
    + },
    + {
    + "ArchStdEvent": "L3D_CACHE"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB_REFILL"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB"
    + },
    + {
    + "ArchStdEvent": "DTLB_WALK"
    + },
    + {
    + "ArchStdEvent": "ITLB_WALK"
    + },
    + {
    + "ArchStdEvent": "LL_CACHE_RD"
    + },
    + {
    + "ArchStdEvent": "LL_CACHE_MISS_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_LMISS_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_WR"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_REFILL_WR"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
    + },
    + {
    + "ArchStdEvent": "L1D_CACHE_INVAL"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB_REFILL_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB_REFILL_WR"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB_RD"
    + },
    + {
    + "ArchStdEvent": "L1D_TLB_WR"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_RD"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_WR"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_REFILL_RD"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_REFILL_WR"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_INVAL"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB_REFILL_RD"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB_REFILL_WR"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB_RD"
    + },
    + {
    + "ArchStdEvent": "L2D_TLB_WR"
    + },
    + {
    + "ArchStdEvent": "L3D_CACHE_RD"
    + },
    + {
    + "ArchStdEvent": "L1I_CACHE_LMISS"
    + },
    + {
    + "ArchStdEvent": "L2D_CACHE_LMISS_RD"
    + },
    + {
    + "ArchStdEvent": "L3D_CACHE_LMISS_RD"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
    new file mode 100644
    index 000000000000..344a2d552ad5
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
    @@ -0,0 +1,47 @@
    +[
    + {
    + "ArchStdEvent": "EXC_TAKEN"
    + },
    + {
    + "ArchStdEvent": "MEMORY_ERROR"
    + },
    + {
    + "ArchStdEvent": "EXC_UNDEF"
    + },
    + {
    + "ArchStdEvent": "EXC_SVC"
    + },
    + {
    + "ArchStdEvent": "EXC_PABORT"
    + },
    + {
    + "ArchStdEvent": "EXC_DABORT"
    + },
    + {
    + "ArchStdEvent": "EXC_IRQ"
    + },
    + {
    + "ArchStdEvent": "EXC_FIQ"
    + },
    + {
    + "ArchStdEvent": "EXC_SMC"
    + },
    + {
    + "ArchStdEvent": "EXC_HVC"
    + },
    + {
    + "ArchStdEvent": "EXC_TRAP_PABORT"
    + },
    + {
    + "ArchStdEvent": "EXC_TRAP_DABORT"
    + },
    + {
    + "ArchStdEvent": "EXC_TRAP_OTHER"
    + },
    + {
    + "ArchStdEvent": "EXC_TRAP_IRQ"
    + },
    + {
    + "ArchStdEvent": "EXC_TRAP_FIQ"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
    new file mode 100644
    index 000000000000..a9edd52843a1
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
    @@ -0,0 +1,80 @@
    +[
    + {
    + "ArchStdEvent": "SW_INCR"
    + },
    + {
    + "ArchStdEvent": "INST_RETIRED"
    + },
    + {
    + "ArchStdEvent": "EXC_RETURN"
    + },
    + {
    + "ArchStdEvent": "CID_WRITE_RETIRED"
    + },
    + {
    + "ArchStdEvent": "INST_SPEC"
    + },
    + {
    + "ArchStdEvent": "TTBR_WRITE_RETIRED"
    + },
    + {
    + "ArchStdEvent": "BR_RETIRED"
    + },
    + {
    + "ArchStdEvent": "BR_MIS_PRED_RETIRED"
    + },
    + {
    + "ArchStdEvent": "OP_RETIRED"
    + },
    + {
    + "ArchStdEvent": "OP_SPEC"
    + },
    + {
    + "ArchStdEvent": "LDREX_SPEC"
    + },
    + {
    + "ArchStdEvent": "STREX_PASS_SPEC"
    + },
    + {
    + "ArchStdEvent": "STREX_FAIL_SPEC"
    + },
    + {
    + "ArchStdEvent": "STREX_SPEC"
    + },
    + {
    + "ArchStdEvent": "LD_SPEC"
    + },
    + {
    + "ArchStdEvent": "ST_SPEC"
    + },
    + {
    + "ArchStdEvent": "DP_SPEC"
    + },
    + {
    + "ArchStdEvent": "ASE_SPEC"
    + },
    + {
    + "ArchStdEvent": "VFP_SPEC"
    + },
    + {
    + "ArchStdEvent": "PC_WRITE_SPEC"
    + },
    + {
    + "ArchStdEvent": "CRYPTO_SPEC"
    + },
    + {
    + "ArchStdEvent": "ISB_SPEC"
    + },
    + {
    + "ArchStdEvent": "DSB_SPEC"
    + },
    + {
    + "ArchStdEvent": "DMB_SPEC"
    + },
    + {
    + "ArchStdEvent": "RC_LD_SPEC"
    + },
    + {
    + "ArchStdEvent": "RC_ST_SPEC"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
    new file mode 100644
    index 000000000000..5aff6e93c1ad
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
    @@ -0,0 +1,23 @@
    +[
    + {
    + "ArchStdEvent": "MEM_ACCESS"
    + },
    + {
    + "ArchStdEvent": "REMOTE_ACCESS"
    + },
    + {
    + "ArchStdEvent": "MEM_ACCESS_RD"
    + },
    + {
    + "ArchStdEvent": "MEM_ACCESS_WR"
    + },
    + {
    + "ArchStdEvent": "UNALIGNED_LD_SPEC"
    + },
    + {
    + "ArchStdEvent": "UNALIGNED_ST_SPEC"
    + },
    + {
    + "ArchStdEvent": "UNALIGNED_LDST_SPEC"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
    new file mode 100644
    index 000000000000..f9fae15f7555
    --- /dev/null
    +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
    @@ -0,0 +1,23 @@
    +[
    + {
    + "ArchStdEvent": "STALL_FRONTEND"
    + },
    + {
    + "ArchStdEvent": "STALL_BACKEND"
    + },
    + {
    + "ArchStdEvent": "STALL"
    + },
    + {
    + "ArchStdEvent": "STALL_SLOT_BACKEND"
    + },
    + {
    + "ArchStdEvent": "STALL_SLOT_FRONTEND"
    + },
    + {
    + "ArchStdEvent": "STALL_SLOT"
    + },
    + {
    + "ArchStdEvent": "STALL_BACKEND_MEM"
    + }
    +]
    diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
    index 1fa58d247132..31a43b5114bc 100644
    --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
    +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
    @@ -33,6 +33,7 @@
    0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
    0x00000000410fd0d0,v1,arm/cortex-a77,core
    0x00000000410fd400,v1,arm/neoverse-v1,core
    +0x00000000410fd410,v1,arm/cortex-a78,core
    0x00000000410fd460,v1,arm/cortex-a510,core
    0x00000000410fd490,v1,arm/neoverse-n2,core
    0x00000000420f5160,v1,cavium/thunderx2,core
    --
    2.25.1
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