| Date | Sun, 13 Mar 2022 15:30:50 +0100 | Subject | Re: [RFC PATCH v5 012/104] KVM: TDX: Define TDX architectural definitions | From | Paolo Bonzini <> |
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On 3/4/22 20:48, isaku.yamahata@intel.com wrote: > From: Isaku Yamahata <isaku.yamahata@intel.com> > > Define architectural definitions for KVM to issue the TDX SEAMCALLs. > > Structures and values that are architecturally defined in the TDX module > specifications the chapter of ABI Reference. > > Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> > --- > arch/x86/kvm/vmx/tdx_arch.h | 158 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 arch/x86/kvm/vmx/tdx_arch.h
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> diff --git a/arch/x86/kvm/vmx/tdx_arch.h b/arch/x86/kvm/vmx/tdx_arch.h > new file mode 100644 > index 000000000000..3824491d22dc > --- /dev/null > +++ b/arch/x86/kvm/vmx/tdx_arch.h > @@ -0,0 +1,158 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* architectural constants/data definitions for TDX SEAMCALLs */ > + > +#ifndef __KVM_X86_TDX_ARCH_H > +#define __KVM_X86_TDX_ARCH_H > + > +#include <linux/types.h> > + > +/* > + * TDX SEAMCALL API function leaves > + */ > +#define TDH_VP_ENTER 0 > +#define TDH_MNG_ADDCX 1 > +#define TDH_MEM_PAGE_ADD 2 > +#define TDH_MEM_SEPT_ADD 3 > +#define TDH_VP_ADDCX 4 > +#define TDH_MEM_PAGE_AUG 6 > +#define TDH_MEM_RANGE_BLOCK 7 > +#define TDH_MNG_KEY_CONFIG 8 > +#define TDH_MNG_CREATE 9 > +#define TDH_VP_CREATE 10 > +#define TDH_MNG_RD 11 > +#define TDH_MR_EXTEND 16 > +#define TDH_MR_FINALIZE 17 > +#define TDH_VP_FLUSH 18 > +#define TDH_MNG_VPFLUSHDONE 19 > +#define TDH_MNG_KEY_FREEID 20 > +#define TDH_MNG_INIT 21 > +#define TDH_VP_INIT 22 > +#define TDH_VP_RD 26 > +#define TDH_MNG_KEY_RECLAIMID 27 > +#define TDH_PHYMEM_PAGE_RECLAIM 28 > +#define TDH_MEM_PAGE_REMOVE 29 > +#define TDH_MEM_TRACK 38 > +#define TDH_MEM_RANGE_UNBLOCK 39 > +#define TDH_PHYMEM_CACHE_WB 40 > +#define TDH_PHYMEM_PAGE_WBINVD 41 > +#define TDH_VP_WR 43 > +#define TDH_SYS_LP_SHUTDOWN 44 > + > +#define TDG_VP_VMCALL_GET_TD_VM_CALL_INFO 0x10000 > +#define TDG_VP_VMCALL_MAP_GPA 0x10001 > +#define TDG_VP_VMCALL_GET_QUOTE 0x10002 > +#define TDG_VP_VMCALL_REPORT_FATAL_ERROR 0x10003 > +#define TDG_VP_VMCALL_SETUP_EVENT_NOTIFY_INTERRUPT 0x10004 > + > +/* TDX control structure (TDR/TDCS/TDVPS) field access codes */ > +#define TDX_NON_ARCH BIT_ULL(63) > +#define TDX_CLASS_SHIFT 56 > +#define TDX_FIELD_MASK GENMASK_ULL(31, 0) > + > +#define __BUILD_TDX_FIELD(non_arch, class, field) \ > + (((non_arch) ? TDX_NON_ARCH : 0) | \ > + ((u64)(class) << TDX_CLASS_SHIFT) | \ > + ((u64)(field) & TDX_FIELD_MASK)) > + > +#define BUILD_TDX_FIELD(class, field) \ > + __BUILD_TDX_FIELD(false, (class), (field)) > + > +#define BUILD_TDX_FIELD_NON_ARCH(class, field) \ > + __BUILD_TDX_FIELD(true, (class), (field)) > + > + > +/* @field is the VMCS field encoding */ > +#define TDVPS_VMCS(field) BUILD_TDX_FIELD(0, (field)) > + > +enum tdx_guest_other_state { > + TD_VCPU_STATE_DETAILS_NON_ARCH = 0x100, > +}; > + > +union tdx_vcpu_state_details { > + struct { > + u64 vmxip : 1; > + u64 reserved : 63; > + }; > + u64 full; > +}; > + > +/* @field is any of enum tdx_guest_other_state */ > +#define TDVPS_STATE(field) BUILD_TDX_FIELD(17, (field)) > +#define TDVPS_STATE_NON_ARCH(field) BUILD_TDX_FIELD_NON_ARCH(17, (field)) > + > +/* Management class fields */ > +enum tdx_guest_management { > + TD_VCPU_PEND_NMI = 11, > +}; > + > +/* @field is any of enum tdx_guest_management */ > +#define TDVPS_MANAGEMENT(field) BUILD_TDX_FIELD(32, (field)) > + > +enum tdx_tdcs_execution_control { > + TD_TDCS_EXEC_TSC_OFFSET = 10, > +}; > + > +/* @field is any of enum tdx_tdcs_execution_control */ > +#define TDCS_EXEC(field) BUILD_TDX_FIELD(17, (field)) > + > +#define TDX_EXTENDMR_CHUNKSIZE 256 > + > +struct tdx_cpuid_value { > + u32 eax; > + u32 ebx; > + u32 ecx; > + u32 edx; > +} __packed; > + > +#define TDX_TD_ATTRIBUTE_DEBUG BIT_ULL(0) > +#define TDX_TD_ATTRIBUTE_PKS BIT_ULL(30) > +#define TDX_TD_ATTRIBUTE_KL BIT_ULL(31) > +#define TDX_TD_ATTRIBUTE_PERFMON BIT_ULL(63) > + > +#define TDX_TD_XFAM_LBR BIT_ULL(15) > +#define TDX_TD_XFAM_AMX (BIT_ULL(17) | BIT_ULL(18)) > + > +/* > + * TD_PARAMS is provided as an input to TDH_MNG_INIT, the size of which is 1024B. > + */ > +struct td_params { > + u64 attributes; > + u64 xfam; > + u32 max_vcpus; > + u32 reserved0; > + > + u64 eptp_controls; > + u64 exec_controls; > + u16 tsc_frequency; > + u8 reserved1[38]; > + > + u64 mrconfigid[6]; > + u64 mrowner[6]; > + u64 mrownerconfig[6]; > + u64 reserved2[4]; > + > + union { > + struct tdx_cpuid_value cpuid_values[0]; > + u8 reserved3[768]; > + }; > +} __packed __aligned(1024); > + > +/* > + * Guest uses MAX_PA for GPAW when set. > + * 0: GPA.SHARED bit is GPA[47] > + * 1: GPA.SHARED bit is GPA[51] > + */ > +#define TDX_EXEC_CONTROL_MAX_GPAW BIT_ULL(0) > + > +/* > + * TDX requires the frequency to be defined in units of 25MHz, which is the > + * frequency of the core crystal clock on TDX-capable platforms, i.e. the TDX > + * module can only program frequencies that are multiples of 25MHz. The > + * frequency must be between 100mhz and 10ghz (inclusive). > + */ > +#define TDX_TSC_KHZ_TO_25MHZ(tsc_in_khz) ((tsc_in_khz) / (25 * 1000)) > +#define TDX_TSC_25MHZ_TO_KHZ(tsc_in_25mhz) ((tsc_in_25mhz) * (25 * 1000)) > +#define TDX_MIN_TSC_FREQUENCY_KHZ (100 * 1000) > +#define TDX_MAX_TSC_FREQUENCY_KHZ (10 * 1000 * 1000) > + > +#endif /* __KVM_X86_TDX_ARCH_H */
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