Messages in this thread | | | From | Prabhakar <> | Subject | [PATCH RFC 0/5] Add IRQC support to RZ/G2UL SoC | Date | Mon, 7 Nov 2022 17:53:00 +0000 |
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series does the following: * Adds IRQC support to the RZ/G2UL SoC. * Includes a fix for pinctrl driver when using GPIO pins as interrupts * Adds PHY interrupt support for ETH{0/1}
Reason for sending it as RFC, as I am introducing new compatible string for RZ/G2UL SoC as there are some differences when compared to RZ/Five: - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt domain) -> RISCV INTC - On the RZ/Five we have additional registers for IRQC block - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC
Cheers, Prabhakar
Lad Prabhakar (5): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts arm64: dts: renesas: r9a07g043[u]: Add IRQC node arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
.../renesas,rzg2l-irqc.yaml | 1 + arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 10 ++++ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 54 +++++++++++++++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +++--- 5 files changed, 84 insertions(+), 9 deletions(-)
-- 2.25.1
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