Messages in this thread Patch in this message | | | From | Claudiu <> | Subject | [PATCH v2 05/28] clk: renesas: rzg2l: fix computation formula | Date | Fri, 29 Sep 2023 08:38:52 +0300 |
| |
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
According to hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf) the computation formula for PLL rate is as follows:
Fout = ((m + k/65536) * Fin) / (p * 2^s)
and k has values in range [-32768, 32767]. Dividing k by 65536 with integer variables leads all the time to zero. Thus we may have slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536.
Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> ---
Changes in v2: - used mul_u64_u32_shr()
drivers/clk/renesas/rzg2l-cpg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 6f50f0329ecf..f411e428196c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -695,18 +695,18 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, struct pll_clk *pll_clk = to_pll(hw); struct rzg2l_cpg_priv *priv = pll_clk->priv; unsigned int val1, val2; - unsigned int mult = 1; - unsigned int div = 1; + u64 rate; if (pll_clk->type != CLK_TYPE_SAM_PLL) return parent_rate; val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); - mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) << SDIV(val2); - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); + rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + (s16)KDIV(val1), + 16 + SDIV(val2)); + + return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1)); } static const struct clk_ops rzg2l_cpg_pll_ops = { -- 2.39.2
| |