Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Wed, 4 Oct 2023 14:37:11 +0200 | Subject | Re: [PATCH v2 12/28] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC |
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On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add documentation for RZ/G3S CPG. RZ/G3S CPG module is almost identical > with the one available in RZ/G2{L, UL} the exception being some core > clocks as follows: > - SD clock is composed by a mux and a divider and the divider > has some limitation (div = 1 cannot be set if mux rate is 800MHz). > - there are 3 SD clocks > - OCTA and TSU clocks are specific to RZ/G3S > - PLL1/4/6 are specific to RZ/G3S with its own computation formula > Even with this RZ/G3S could use the same bindings as RZ/G2L. > > Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse > Generator (CPG) core clocks, module clocks and resets were added. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > > Changes in v2: > - collected Rob's tag > - squashed with > [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets > from v1 > - updated commit message to reflect that bindings were also added to > this patch > - removed R9A08G045_USB_SCLK > - @Geert: please note I haven't collected your Rb tag as I did the squash
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in a branch shared by renesas-clk and renesas-dts for v6.7.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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