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    Subject[PATCH v2 24/28] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC SoM
    Date
    From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

    Add initial support for RZ/G3S SMARC SoM. The following devices available
    on SoM were added to this initial device tree:

    - RZ/G3S SoC: Renesas R9A08G045S33GBG
    - Clock Generator (only 24MHz output): Renesas 5L35023B
    - 1GiB LPDDR4 SDRAM: Micron MT53D512M16D1DS-046
    - 64GB eMMC Flash (though SD ch0): Micron MTFC64GBCAQTC

    SD channel 0 of RZ/G3S is connected to an uSD card interface
    and an eMMC. The selection b/w them is done though a hardware switch.
    The DT will select b/w uSD and eMMC though SW_SD0_DEV_SEL build flag.

    Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
    ---

    Changes in v2:
    - s/Carrier-II SoM/SoM in patch title
    - listed in commit description only devices addressed by this initial dtsi
    - s/8G LPDDR4/1GiB LPDDR4 in commit description
    - removed sd0-pwr-en-hog node and use specific GPIO in vcc_sdhi0 regulator
    - added SoM compatible:
    compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";

    .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 142 ++++++++++++++++++
    1 file changed, 142 insertions(+)
    create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi

    diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
    new file mode 100644
    index 000000000000..185ca8289a35
    --- /dev/null
    +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
    @@ -0,0 +1,142 @@
    +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +/*
    + * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
    + *
    + * Copyright (C) 2023 Renesas Electronics Corp.
    + */
    +
    +#include <dt-bindings/gpio/gpio.h>
    +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
    +
    +/*
    + * Signals of SW_CONFIG switches:
    + * @SW_SD0_DEV_SEL:
    + * 0 - SD0 is connected to eMMC
    + * 1 - SD0 is connected to uSD0 card
    + */
    +#define SW_SD0_DEV_SEL 1
    +
    +/ {
    + compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
    +
    + aliases {
    + mmc0 = &sdhi0;
    + };
    +
    + chosen {
    + bootargs = "ignore_loglevel";
    + stdout-path = "serial0:115200n8";
    + };
    +
    + memory@48000000 {
    + device-type = "memory";
    + /* First 128MB is reserved for secure area. */
    + reg = <0x0 0x48000000 0x0 0x38000000>;
    + };
    +
    + vcc_sdhi0: regulator0 {
    + compatible = "regulator-fixed";
    + regulator-name = "SDHI0 Vcc";
    + regulator-min-microvolt = <3300000>;
    + regulator-max-microvolt = <3300000>;
    + gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
    + enable-active-high;
    + };
    +
    +#if SW_SD0_DEV_SEL
    + vccq_sdhi0: regulator1 {
    + compatible = "regulator-gpio";
    + regulator-name = "SDHI0 VccQ";
    + regulator-min-microvolt = <1800000>;
    + regulator-max-microvolt = <3300000>;
    + gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
    + gpios-states = <1>;
    + states = <3300000 1>, <1800000 0>;
    + };
    +#else
    + reg_1p8v: regulator1 {
    + compatible = "regulator-fixed";
    + regulator-name = "fixed-1.8V";
    + regulator-min-microvolt = <1800000>;
    + regulator-max-microvolt = <1800000>;
    + regulator-boot-on;
    + regulator-always-on;
    + };
    +#endif
    +};
    +
    +&extal_clk {
    + clock-frequency = <24000000>;
    +};
    +
    +#if SW_SD0_DEV_SEL
    +/* SD0 slot */
    +&sdhi0 {
    + pinctrl-0 = <&sdhi0_pins>;
    + pinctrl-1 = <&sdhi0_uhs_pins>;
    + pinctrl-names = "default", "state_uhs";
    + vmmc-supply = <&vcc_sdhi0>;
    + vqmmc-supply = <&vccq_sdhi0>;
    + bus-width = <4>;
    + sd-uhs-sdr50;
    + sd-uhs-sdr104;
    + max-frequency = <125000000>;
    + status = "okay";
    +};
    +#else
    +/* eMMC */
    +&sdhi0 {
    + pinctrl-0 = <&sdhi0_emmc_pins>;
    + pinctrl-1 = <&sdhi0_emmc_pins>;
    + pinctrl-names = "default", "state_uhs";
    + vmmc-supply = <&vcc_sdhi0>;
    + vqmmc-supply = <&reg_1p8v>;
    + bus-width = <8>;
    + mmc-hs200-1_8v;
    + non-removable;
    + fixed-emmc-driver-type = <1>;
    + max-frequency = <125000000>;
    + status = "okay";
    +};
    +#endif
    +
    +&pinctrl {
    + sdhi0_pins: sd0 {
    + data {
    + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
    + power-source = <3300>;
    + };
    +
    + ctrl {
    + pins = "SD0_CLK", "SD0_CMD";
    + power-source = <3300>;
    + };
    +
    + cd {
    + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
    + };
    + };
    +
    + sdhi0_uhs_pins: sd0-uhs {
    + data {
    + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
    + power-source = <1800>;
    + };
    +
    + ctrl {
    + pins = "SD0_CLK", "SD0_CMD";
    + power-source = <1800>;
    + };
    +
    + cd {
    + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
    + };
    + };
    +
    + sdhi0_emmc_pins: sd0-emmc {
    + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
    + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
    + "SD0_CLK", "SD0_CMD", "SD0_RST#";
    + power-source = <1800>;
    + };
    +};
    --
    2.39.2
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