| From | David Wretman <> | Subject | [RFC PATCH net-next 5/6] microchip: lan865x: add driver support for Microchip's LAN865X MACPHY | Date | Fri, 15 Sep 2023 15:01:19 +0200 |
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--- On Fri, Sep 08, 2023 at 07:59:18PM +0530, Parthiban Veerasooran wrote: > The LAN8650/1 is designed to conform to the OPEN Alliance 10BASE‑T1x > MAC‑PHY Serial Interface specification, Version 1.1. The IEEE Clause 4 > MAC integration provides the low pin count standard SPI interface to any > microcontroller therefore providing Ethernet functionality without > requiring MAC integration within the microcontroller. The LAN8650/1 > operates as an SPI client supporting SCLK clock rates up to a maximum of > 25 MHz. This SPI interface supports the transfer of both data (Ethernet > frames) and control (register access). > > By default, the chunk data payload is 64 bytes in size. A smaller payload > data size of 32 bytes is also supported and may be configured in the > Chunk Payload Size (CPS) field of the Configuration 0 (OA_CONFIG0) > register. Changing the chunk payload size requires the LAN8650/1 be reset > and shall not be done during normal operation. > > The Ethernet Media Access Controller (MAC) module implements a 10 Mbps > half duplex Ethernet MAC, compatible with the IEEE 802.3 standard. > 10BASE-T1S physical layer transceiver integrated into the LAN8650/1. The > PHY and MAC are connected via an internal Media Independent Interface > (MII). > > Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Hi Parthiban,
Thanks for these patches.
One thing I am missing is settings for PLCA parameters. I feel that the driver is a bit lacking as long as this is missing.
Adding support for the ethtool plca options would make this much more complete.
Regards, David
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