Messages in this thread | | | Date | Fri, 27 Jan 2023 22:53:05 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions |
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Yo Atish,
On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote: > This patch fixes/improve few minor things in SBI PMU extension > definition. > > 1. Align all the firmware event names.
> @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t { > SBI_PMU_FW_IPI_RECVD = 7, > - SBI_PMU_FW_FENCE_I_RECVD = 9, > + SBI_PMU_FW_FENCE_I_RCVD = 9, > SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
Alignment looks incomplete to me! Looks like you went from 2 RECVD and 1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of these: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15
Thanks, Conor.
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