Messages in this thread Patch in this message | | | From | Yazen Ghannam <> | Subject | [PATCH 07/18] EDAC/amd64: Add read_base_mask() into pvt->ops | Date | Mon, 9 May 2022 14:55:23 +0000 |
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From: Muralidhara M K <muralidhara.mk@amd.com>
GPU Nodes will need to set the read the Base and Mask values differently than existing systems. A function pointer should be used rather than introduce another branching condition.
Prepare for this by adding read_base_mask() to pvt->ops and set it as needed based on currently supported systems.
Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs).
Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs).
Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- drivers/edac/amd64_edac.c | 11 +++++------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f8cd89278753..6e26bbb73f81 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1507,7 +1507,7 @@ static void umc_prep_chip_selects(struct amd64_pvt *pvt) } } -static void read_umc_base_mask(struct amd64_pvt *pvt) +static void umc_read_base_mask(struct amd64_pvt *pvt) { u32 umc_base_reg, umc_base_reg_sec; u32 umc_mask_reg, umc_mask_reg_sec; @@ -1561,13 +1561,10 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) /* * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers */ -static void read_dct_base_mask(struct amd64_pvt *pvt) +static void dct_read_base_mask(struct amd64_pvt *pvt) { int cs; - if (pvt->umc) - return read_umc_base_mask(pvt); - for_each_chip_select(cs, 0, pvt) { int reg0 = DCSB0 + (cs * 4); int reg1 = DCSB1 + (cs * 4); @@ -3303,7 +3300,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) skip: pvt->ops->prep_chip_selects(pvt); - read_dct_base_mask(pvt); + pvt->ops->read_base_mask(pvt); determine_memory_type(pvt); @@ -3765,6 +3762,7 @@ static struct low_ops umc_ops = { .early_channel_count = umc_early_channel_count, .dbam_to_cs = umc_addr_mask_to_cs_size, .prep_chip_selects = umc_prep_chip_selects, + .read_base_mask = umc_read_base_mask, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3773,6 +3771,7 @@ static struct low_ops dct_ops = { .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, .dbam_to_cs = f16_dbam_to_chip_select, .prep_chip_selects = dct_prep_chip_selects, + .read_base_mask = dct_read_base_mask, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 0a7738df396f..c81cc7f5fc96 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -469,6 +469,7 @@ struct low_ops { int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct, unsigned int cs_mode, int cs_mask_nr); void (*prep_chip_selects)(struct amd64_pvt *pvt); + void (*read_base_mask)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1
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