Messages in this thread Patch in this message | | | From | Yazen Ghannam <> | Subject | [PATCH 13/18] EDAC/amd64: Add determine_edac_ctl_cap() into pvt->ops | Date | Mon, 9 May 2022 14:55:29 +0000 |
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From: Muralidhara M K <muralidhara.mk@amd.com>
GPU Nodes will have different criteria for checking the EDAC capabilities of a controller. A function pointer should be used rather than introduce another branching condition.
Prepare for this by adding determine_edac_ctl_cap() to pvt->ops and set it as needed based on currently supported systems.
Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs).
Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs).
Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- drivers/edac/amd64_edac.c | 24 ++++++++++++++---------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0bc9a3846773..b99eaa73131e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3697,7 +3697,17 @@ static bool umc_ecc_enabled(struct amd64_pvt *pvt) } static inline void -f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +dct_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +{ + if (pvt->nbcap & NBCAP_SECDED) + mci->edac_ctl_cap |= EDAC_FLAG_SECDED; + + if (pvt->nbcap & NBCAP_CHIPKILL) + mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; +} + +static inline void +umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) { u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; @@ -3734,15 +3744,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; - if (pvt->umc) { - f17h_determine_edac_ctl_cap(mci, pvt); - } else { - if (pvt->nbcap & NBCAP_SECDED) - mci->edac_ctl_cap |= EDAC_FLAG_SECDED; - - if (pvt->nbcap & NBCAP_CHIPKILL) - mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; - } + pvt->ops->determine_edac_ctl_cap(mci, pvt); mci->edac_cap = pvt->ops->determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; @@ -3765,6 +3767,7 @@ static struct low_ops umc_ops = { .read_mc_regs = umc_read_mc_regs, .ecc_enabled = umc_ecc_enabled, .determine_edac_cap = umc_determine_edac_cap, + .determine_edac_ctl_cap = umc_determine_edac_ctl_cap, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3779,6 +3782,7 @@ static struct low_ops dct_ops = { .read_mc_regs = dct_read_mc_regs, .ecc_enabled = dct_ecc_enabled, .determine_edac_cap = dct_determine_edac_cap, + .determine_edac_ctl_cap = dct_determine_edac_ctl_cap, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index bfe48492a0ba..15521adec9b5 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -475,6 +475,7 @@ struct low_ops { void (*read_mc_regs)(struct amd64_pvt *pvt); bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); + void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1
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