Messages in this thread | | | Subject | Re: [PATCH v1 3/4] soc: imx: imx8m-blk-ctrl: Add reset bits for mipi dsi phy | From | Lucas Stach <> | Date | Mon, 02 May 2022 12:13:27 +0200 |
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Am Montag, dem 02.05.2022 um 12:02 +0200 schrieb Viraj Shah: > As per reference manual page 3903, bit 16 (GPR_MIPI_S_RESETN) > as well as 17 (GPR_MIPI_M_RESETN) are the reset masks for mipi phy reset > mask.
Nack. The MIPI-S reset is used for the CSI receiver and is already handled by the appropriate power domain.
Regards, Lucas
> > Signed-off-by: Viraj Shah <viraj.shah@linutronix.de> > --- > drivers/soc/imx/imx8m-blk-ctrl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index ca63fd30e70a..d7638b7fa99d 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -502,7 +502,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] > .gpc_name = "mipi-dsi", > .rst_mask = BIT(5), > .clk_mask = BIT(8) | BIT(9), > - .mipi_phy_rst_mask = BIT(17), > + .mipi_phy_rst_mask = BIT(17) | BIT(16), > }, > [IMX8MM_DISPBLK_PD_MIPI_CSI] = { > .name = "dispblk-mipi-csi",
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