Messages in this thread | | | Subject | Re: [PATCH v1 2/4] soc: imx: imx8m-blk-ctrl: Display Power ON sequence | From | Lucas Stach <> | Date | Mon, 02 May 2022 12:12:22 +0200 |
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Am Montag, dem 02.05.2022 um 12:02 +0200 schrieb Viraj Shah: > Enable the dispmix software clock and release the resets > as shown in the 5.2.9.5 section of reference manual. > > Signed-off-by: Viraj Shah <viraj.shah@linutronix.de> > --- > drivers/soc/imx/imx8m-blk-ctrl.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index 122f9c884b38..ca63fd30e70a 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -99,7 +99,10 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) > dev_err(bc->dev, "failed to enable clocks\n"); > goto bus_put; > } > - regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); > + /* As per section 5.2.9.5 of reference manual imx-8MMini-yhsc.pdf, > + * enable dispmix sft clock to power on the display > + */ > + regmap_write(bc->regmap, BLK_CLK_EN, 0x1FFF);
Nack. The only clock that needs to be handled here is the ADB clock for the handshake. All other clocks are enabled by the virtual power domains provided by this blk-ctrl driver when the peripheral power up.
Regards, Lucas
> > /* power up upstream GPC domain */ > ret = pm_runtime_get_sync(domain->power_dev); > @@ -112,7 +115,7 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) > udelay(5); > > /* release reset */ > - regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); > + regmap_write(bc->regmap, BLK_SFT_RSTN, 0x7F); > if (data->mipi_phy_rst_mask) > regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); >
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