Messages in this thread | | | From | Mike Leach <> | Date | Tue, 12 Apr 2022 11:41:10 +0100 | Subject | Re: [PATCH v3 14/15] coresight: etm4x: Cleanup TRCBBCTLR register accesses |
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On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@arm.com> wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 4 ++-- > drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 25f76a656308..3ae6f4432646 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -707,10 +707,10 @@ static ssize_t bb_ctrl_store(struct device *dev, > * individual range comparators. If include then at least 1 > * range must be selected. > */ > - if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) > + if ((val & TRCBBCTLR_MODE) && (FIELD_GET(TRCBBCTLR_RANGE_MASK, val) == 0)) > return -EINVAL; > > - config->bb_ctrl = val & GENMASK(8, 0); > + config->bb_ctrl = val & (TRCBBCTLR_MODE | TRCBBCTLR_RANGE_MASK); > return size; > } > static DEVICE_ATTR_RW(bb_ctrl); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 3b81c104a44b..15704982357f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -220,6 +220,9 @@ > > #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) > > +#define TRCBBCTLR_MODE BIT(8) > +#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 >
Reviewed-by: Mike Leach <mike.leach@linaro.org>
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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