Messages in this thread | | | From | Mike Leach <> | Date | Tue, 12 Apr 2022 10:18:18 +0100 | Subject | Re: [PATCH v3 08/15] coresight: etm4x: Cleanup TRCSTALLCTLR register accesses |
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On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@arm.com> wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ > drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ > 2 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 2d29e9daf515..cd24590ea38a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -397,22 +397,22 @@ static ssize_t mode_store(struct device *dev, > > /* bit[8], Instruction stall bit */ > if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) > - config->stall_ctrl |= BIT(8); > + config->stall_ctrl |= TRCSTALLCTLR_ISTALL; > else > - config->stall_ctrl &= ~BIT(8); > + config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL; > > /* bit[10], Prioritize instruction trace bit */ > if (config->mode & ETM_MODE_INSTPRIO) > - config->stall_ctrl |= BIT(10); > + config->stall_ctrl |= TRCSTALLCTLR_INSTPRIORITY; > else > - config->stall_ctrl &= ~BIT(10); > + config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY; > > /* bit[13], Trace overflow prevention bit */ > if ((config->mode & ETM_MODE_NOOVERFLOW) && > (drvdata->nooverflow == true)) > - config->stall_ctrl |= BIT(13); > + config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW; > else > - config->stall_ctrl &= ~BIT(13); > + config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW; > > /* bit[9] Start/stop logic control bit */ > if (config->mode & ETM_MODE_VIEWINST_STARTSTOP) > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index cbba46f14ada..36934056a5dc 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -196,6 +196,10 @@ > #define TRCEVENTCTL1R_ATB BIT(11) > #define TRCEVENTCTL1R_LPOVERRIDE BIT(12) > > +#define TRCSTALLCTLR_ISTALL BIT(8) > +#define TRCSTALLCTLR_INSTPRIORITY BIT(10) > +#define TRCSTALLCTLR_NOOVERFLOW BIT(13) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 >
Reviewed-by: Mike Leach <mike.leach@linaro.org>
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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