Messages in this thread | | | From | Mike Leach <> | Date | Tue, 12 Apr 2022 11:32:48 +0100 | Subject | Re: [PATCH v3 12/15] coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses |
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On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@arm.com> wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 88353f8ba414..87299e99dabb 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nr_ss_cmp; i++) { > /* always clear status bit on restart if using single-shot */ > if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > - config->ss_status[i] &= ~BIT(31); > + config->ss_status[i] &= ~TRCSSCSRn_STATUS; > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > if (etm4x_sspcicrn_present(drvdata, i)) > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 29188b1a4646..7dd7636fc2a7 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1792,9 +1792,9 @@ static ssize_t sshot_ctrl_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > - config->ss_ctrl[idx] = val & GENMASK(24, 0); > + config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); > /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~BIT(31); > + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > spin_unlock(&drvdata->spinlock); > return size; > } > @@ -1844,7 +1844,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, > idx = config->ss_idx; > config->ss_pe_cmp[idx] = val & GENMASK(7, 0); > /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~BIT(31); > + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > spin_unlock(&drvdata->spinlock); > return size; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 802ddbe2eecd..b4217eaab450 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -214,6 +214,10 @@ > #define TRCACATRn_CONTEXTTYPE_VMID BIT(3) > #define TRCACATRn_CONTEXT_MASK GENMASK(6, 4) > #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) > + > +#define TRCSSCSRn_STATUS BIT(31) > +#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 >
Reviewed-by: Mike Leach <mike.leach@linaro.org>
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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