Messages in this thread | | | From | Mike Leach <> | Date | Tue, 12 Apr 2022 09:30:23 +0100 | Subject | Re: [PATCH v3 02/15] coresight: etm4x: Cleanup TRCIDR2 register accesses |
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On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@arm.com> wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 9120390a7613..fd44231e9d8a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1116,11 +1116,11 @@ static void etm4_init_arch_data(void *info) > /* maximum size of resources */ > etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); > /* CIDSIZE, bits[9:5] Indicates the Context ID size */ > - drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); > + drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); > /* VMIDSIZE, bits[14:10] Indicates the VMID size */ > - drvdata->vmid_size = BMVAL(etmidr2, 10, 14); > + drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); > /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ > - drvdata->ccsize = BMVAL(etmidr2, 25, 28); > + drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); > > etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); > /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 300741fbc0de..cfdf966016b7 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -143,6 +143,10 @@ > #define TRCIDR0_QSUPP_MASK GENMASK(16, 15) > #define TRCIDR0_TSSIZE_MASK GENMASK(28, 24) > > +#define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5) > +#define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10) > +#define TRCIDR2_CCSIZE_MASK GENMASK(28, 25) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 >
Reviewed-by: Mike Leach <mike.leach@linaro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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