Messages in this thread | | | Date | Tue, 18 May 2021 23:54:31 -0700 | From | Drew Fustini <> | Subject | Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support |
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On Wed, May 19, 2021 at 08:06:17AM +0200, Christoph Hellwig wrote: > On Wed, May 19, 2021 at 02:05:00PM +0800, Guo Ren wrote: > > Since the existing RISC-V ISA cannot solve this problem, it is better > > to provide some configuration for the SOC vendor to customize. > > We've been talking about this problem for close to five years. So no, > if you don't manage to get the feature into the ISA it can't be > supported.
Isn't it a good goal for Linux to support the capabilities present in the SoC that a currently being fab'd?
I believe the CMO group only started last year [1] so the RV64GC SoCs that are going into mass production this year would not have had the opporuntiy of utilizing any RISC-V ISA extension for handling cache management.
Thanks, Drew
[1] https://github.com/riscv/riscv-CMOs
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