Messages in this thread | | | From | Guo Ren <> | Date | Sat, 22 May 2021 08:36:08 +0800 | Subject | Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support |
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On Wed, May 19, 2021 at 3:15 PM Anup Patel <anup@brainfault.org> wrote: > > On Wed, May 19, 2021 at 12:24 PM Drew Fustini <drew@beagleboard.org> wrote: > > > > On Wed, May 19, 2021 at 08:06:17AM +0200, Christoph Hellwig wrote: > > > On Wed, May 19, 2021 at 02:05:00PM +0800, Guo Ren wrote: > > > > Since the existing RISC-V ISA cannot solve this problem, it is better > > > > to provide some configuration for the SOC vendor to customize. > > > > > > We've been talking about this problem for close to five years. So no, > > > if you don't manage to get the feature into the ISA it can't be > > > supported. > > > > Isn't it a good goal for Linux to support the capabilities present in > > the SoC that a currently being fab'd? > > > > I believe the CMO group only started last year [1] so the RV64GC SoCs > > that are going into mass production this year would not have had the > > opporuntiy of utilizing any RISC-V ISA extension for handling cache > > management. > > The current Linux RISC-V policy is to only accept patches for frozen or > ratified ISA specs. > (Refer, Documentation/riscv/patch-acceptance.rst) > > This means even if emulate CMO instructions in OpenSBI, the Linux > patches won't be taken by Palmer because CMO specification is > still in draft stage. Before CMO specification release, could we use a sbi_ecall to solve the current problem? This is not against the specification, when CMO is ready we could let users choose to use the new CMO in Linux.
From a tech view, CMO trap emulation is the same as sbi_ecall.
> > Also, we all know how much time it takes for RISCV international > to freeze some spec. Judging by that we are looking at another > 3-4 years at minimum. > > Regards, > Anup
-- Best Regards Guo Ren
ML: https://lore.kernel.org/linux-csky/
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