Messages in this thread | | | Date | Thu, 11 Jun 2020 09:58:50 +0100 | From | Russell King - ARM Linux admin <> | Subject | Re: [PATCH 2/2] net: dsa: qca8k: Improve SGMII interface handling |
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On Wed, Jun 10, 2020 at 08:15:13PM +0100, Jonathan McDowell wrote: > This patch improves the handling of the SGMII interface on the QCA8K > devices. Previously the driver did no configuration of the port, even if > it was selected. We now configure it up in the appropriate > PHY/MAC/Base-X mode depending on what phylink tells us we are connected > to and ensure it is enabled. > > Tested with a device where the CPU connection is RGMII (i.e. the common > current use case) + one where the CPU connection is SGMII. I don't have > any devices where the SGMII interface is brought out to something other > than the CPU. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > --- > drivers/net/dsa/qca8k.c | 28 +++++++++++++++++++++++++++- > drivers/net/dsa/qca8k.h | 13 +++++++++++++ > 2 files changed, 40 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > index dcd9e8fa99b6..33e62598289e 100644 > --- a/drivers/net/dsa/qca8k.c > +++ b/drivers/net/dsa/qca8k.c > @@ -681,7 +681,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, > const struct phylink_link_state *state) > { > struct qca8k_priv *priv = ds->priv; > - u32 reg; > + u32 reg, val; > > switch (port) { > case 0: /* 1st CPU port */ > @@ -740,6 +740,32 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, > case PHY_INTERFACE_MODE_1000BASEX: > /* Enable SGMII on the port */ > qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); > + > + /* Enable/disable SerDes auto-negotiation as necessary */ > + val = qca8k_read(priv, QCA8K_REG_PWS); > + if (phylink_autoneg_inband(mode)) > + val &= ~QCA8K_PWS_SERDES_AEN_DIS; > + else > + val |= QCA8K_PWS_SERDES_AEN_DIS; > + qca8k_write(priv, QCA8K_REG_PWS, val); > + > + /* Configure the SGMII parameters */ > + val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL); > + > + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | > + QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; > + > + val &= ~QCA8K_SGMII_MODE_CTRL_MASK; > + if (dsa_is_cpu_port(ds, port)) { > + /* CPU port, we're talking to the CPU MAC, be a PHY */ > + val |= QCA8K_SGMII_MODE_CTRL_PHY; > + } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { > + val |= QCA8K_SGMII_MODE_CTRL_MAC; > + } else { > + val |= QCA8K_SGMII_MODE_CTRL_BASEX; > + } > + > + qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
Ah, here it is! Hmm, I suppose as the two patches will be applied together, it's fine to split it like this.
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC for 0.8m (est. 1762m) line in suburbia: sync at 13.1Mbps down 503kbps up
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