Messages in this thread | | | Subject | Re: [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate | From | Stephen Boyd <> | Date | Sat, 19 Dec 2020 15:32:06 -0800 |
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Quoting Claudiu Beznea (2020-11-19 07:43:14) > On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and > CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is > also changed by DVFS to avoid over/under clocking of MCK0 consumers. > The lower limit is changed to be able to set MCK0 accordingly by > DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > ---
Applied to clk-next
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