Messages in this thread Patch in this message | | | Date | Tue, 19 May 2015 00:00:55 -0000 | From | Thomas Gleixner <> | Subject | [patch 4/6] x86, perf, cqm: Avoid pointless msr write |
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If the usage counter is non-zero there is no point to update the rmid in the PQR MSR.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/kernel/cpu/perf_event_intel_cqm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c =================================================================== --- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c +++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c @@ -974,10 +974,12 @@ static void intel_cqm_event_start(struct event->hw.cqm_state &= ~PERF_HES_STOPPED; - if (state->cnt++) - WARN_ON_ONCE(state->rmid != rmid); - else + if (state->cnt++) { + if (!WARN_ON_ONCE(state->rmid != rmid)) + return; + } else { WARN_ON_ONCE(state->rmid); + } state->rmid = rmid; /*
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