Messages in this thread | | | Date | Tue, 19 May 2015 14:59:18 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state |
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On Tue, 19 May 2015, Matt Fleming wrote: > On Tue, 19 May, at 12:00:58AM, Thomas Gleixner wrote: > > closid (CLass Of Service ID) is used for the Class based Cache > > Allocation Technology (CAT). Add explicit storage to the per cpu cache > > for it, so it can be used later with the CAT support (requires to move > > the per cpu data). > > > > While at it: > > > > - Rename the structure to intel_pqr_state which reflects the actual > > purpose of the struct: Cache values which go into the PQR MSR > > > > - Rename 'cnt' to rmid_usecnt which reflects the actual purpose of > > the counter. > > > > - Document the structure and the struct members. > > > > Signed-off-by: Thomas Gleixner <tglx@linutronix.de> > > --- > > arch/x86/kernel/cpu/perf_event_intel_cqm.c | 50 +++++++++++++++-------------- > > 1 file changed, 27 insertions(+), 23 deletions(-) > > > > Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c > > =================================================================== > > --- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c > > +++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c > > @@ -16,18 +16,32 @@ > > static unsigned int cqm_max_rmid = -1; > > static unsigned int cqm_l3_scale; /* supposedly cacheline size */ > > > > -struct intel_cqm_state { > > +/** > > + * struct intel_pqr_state - State cache for the PQR MSR > > + * @rmid: The cached Resource Monitoring ID > > + * @closid: The cached Class Of Service ID > > + * @usecnt: The usage counter for rmid > > + * > > Typo? Should be @rmid_usecnt.
Indeed.
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