| From | Geert Uytterhoeven <> | Date | Fri, 15 Sep 2023 13:58:18 +0200 | Subject | Re: [PATCH 20/37] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC |
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On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add documentation for RZ/G3S CPG. RZ/G3S CPG module is almost identical > with the one available in RZ/G2{L, UL} the exception being some core > clocks as follows: > - SD clock is composed by a mux and a divider and the divider > has some limitation (div = 1 cannot be set if mux rate is 800MHz). > - there are 3 SD clocks > - OCTA and TSU clocks are specific to RZ/G3S > - PLL1/4/6 are specific to RZ/G3S with its own computation formula > Even with this RZ/G3S could use the same bindings as RZ/G2L. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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