Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 14 Sep 2023 15:58:05 +0200 | Subject | Re: [PATCH 15/37] clk: renesas: rzg2l: add support for RZ/G3S PLL |
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Hi Claudiu,
On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add support for reading the frequency of PLL1/4/6 available on RZ/G3S. > The computation formula for PLL frequency is as follows: > Fout = (nir + nfr / 4096) * Fin / (mr * pr) > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -718,11 +718,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = { > .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate, > }; > > +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct pll_clk *pll_clk = to_pll(hw); > + struct rzg2l_cpg_priv *priv = pll_clk->priv; > + u32 nir, nfr, mr, pr, val; > + u64 rate; > + > + if (pll_clk->type != CLK_TYPE_G3S_SAM_PLL) > + return parent_rate; > + > + val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); > + > + pr = 1 << FIELD_GET(GENMASK(28, 26), val);
Please add defines for the various GENMASK(...) fields.
> + /* Hardware interprets values higher than 8 as p = 16. */ > + if (pr > 8) > + pr = 16; > + > + mr = FIELD_GET(GENMASK(25, 22), val) + 1; > + nir = FIELD_GET(GENMASK(21, 13), val) + 1; > + nfr = FIELD_GET(GENMASK(12, 1), val); > + > + rate = DIV_ROUND_CLOSEST_ULL((u64)parent_rate * nfr, 4096); > + rate += (u64)parent_rate * nir;
When rewriting the formula as:
Fout = (4096 * nir + nfr) * Fin / (4096 * mr * pr)
you can simplify to:
rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12);
> + return DIV_ROUND_CLOSEST_ULL(rate, (mr + pr));
mr * pr
> +}
> --- a/drivers/clk/renesas/rzg2l-cpg.h > +++ b/drivers/clk/renesas/rzg2l-cpg.h > @@ -102,6 +102,7 @@ enum clk_types { > CLK_TYPE_IN, /* External Clock Input */ > CLK_TYPE_FF, /* Fixed Factor Clock */ > CLK_TYPE_SAM_PLL, > + CLK_TYPE_G3S_SAM_PLL,
CLK_TYPE_G3S_PLL, as the documentation doesn't use SAM?
> > /* Clock with divider */ > CLK_TYPE_DIV, > @@ -129,6 +130,8 @@ enum clk_types { > DEF_TYPE(_name, _id, _type, .parent = _parent) > #define DEF_SAMPLL(_name, _id, _parent, _conf) \ > DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) > +#define DEF_G3S_SAMPLL(_name, _id, _parent, _conf) \
DEF_G3S_PLL
> + DEF_TYPE(_name, _id, CLK_TYPE_G3S_SAM_PLL, .parent = _parent, .conf = _conf) > #define DEF_INPUT(_name, _id) \ > DEF_TYPE(_name, _id, CLK_TYPE_IN) > #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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