Messages in this thread | | | Date | Fri, 28 Jul 2023 16:22:19 +0100 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH v2 net 2/2] net: stmmac: dwmac-imx: pause the TXC clock in fixed-link |
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On Thu, Jul 27, 2023 at 01:36:45PM -0500, Andrew Halaney wrote: > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c > > index 53ee5a42c071..e7819960128e 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c > > @@ -40,6 +40,9 @@ > > #define DMA_BUS_MODE 0x00001000 > > #define DMA_BUS_MODE_SFT_RESET (0x1 << 0) > > #define RMII_RESET_SPEED (0x3 << 14) > > +#define MII_RESET_SPEED (0x2 << 14) > > +#define RGMII_RESET_SPEED (0x0 << 14) > > +#define CTRL_SPEED_MASK (0x3 << 14) > > GENMASK() would be cleaner, as well as BIT() usage, but I do see > the driver currently does shifts.. so /me shrugs
BIT() is only useful for single-bit items, not for use with bitfields, and their use with bitfields just makes the whole thing perverse.
#define CTRL_SPEED_MASK GENMASK(15, 14) #define CTRL_SPEED_RGMII_RESET 0 #define CTRL_SPEED_MII_RESET 2 #define CTRL_SPEED_RMII_RESET 3
and then its use:
FIELD_PREP(CTRL_SPEED_MASK, CTRL_SPEED_RGMII_RESET) or FIELD_PREP(CTRL_SPEED_MASK, CTRL_SPEED_MII_RESET) or FIELD_PREP(CTRL_SPEED_MASK, CTRL_SPEED_RMII_RESET)
alternatively:
if (iface == MX93_GPR_ENET_QOS_INTF_SEL_RMII) speed = CTRL_SPEED_RMII_RESET; else (iface == MX93_GPR_ENET_QOS_INTF_SEL_MII) speed = CTRL_SPEED_MII_RESET; else speed = CTRL_SPEED_RGMII_RESET;
old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); ctrl = old_ctrl & ~CTRL_SPEED_MASK; ctrl |= FIELD_PREP(CTRL_SPEED_MASK, speed); writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
> I don't have any documentation for the registers here, and as you can > see I'm an amateur with respect to memory ordering based on my prior > comment. > > But you: > > 1. Read intf_reg_off into variable iface > 2. Write the RESET_SPEED for the appropriate mode to MAC_CTRL_REG > 3. wmb() to ensure that write goes through
I wonder about whether that wmb() is required. If the mapping is device-like rather than memory-like, the write should be committed before the read that regmap_update_bits() does according to the ARM memory model. Maybe a bit of information about where this barrier has come from would be good, and maybe getting it reviewed by the arm64 barrier specialist, Will Deacon. :)
wmb() is normally required to be paired with a rmb(), but we're not talking about system memory here, so I also wonder whether wmb() is the correct barrier to use.
Adding Will.
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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