Messages in this thread | | | From | Michael Walle <> | Subject | [PATCH V3 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing | Date | Fri, 5 May 2023 09:33:59 +0200 |
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> The DPHY timings are currently hard coded. Since the input > clock can be variable, the phy timings need to be variable > too. Add an additional variable to the driver data to enable > this feature to prevent breaking boards that don't support it. > > The phy_mipi_dphy_get_default_config function configures the > DPHY timings in pico-seconds, and a small macro converts those > timings into clock cycles based on the pixel clock rate.
This actually fixes a bug with the DSI84 bridge on our boards. The hardcoded settings will violate the D-PHY spec timings for lower frequencies, esp. the Ths_prepare+Ths_zero timing. Thus, the bridge will read a wrong HS sync sequence and set it's internal SoT error bit (and don't generate any RGB signals on the LVDS side).
Tested-by: Michael Walle <michael@walle.cc>
Thanks! -michael
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