Messages in this thread Patch in this message | | | From | arinc9.unal@gmail ... | Subject | [PATCH net 4/7] net: dsa: mt7530: set both CPU port interfaces to PHY_INTERFACE_MODE_NA | Date | Sun, 26 Mar 2023 17:08:15 +0300 |
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From: Arınç ÜNAL <arinc.unal@arinc9.com>
Set interfaces of both CPU ports to PHY_INTERFACE_MODE_NA. Either phylink or mt7530_setup_port5() on mt7530_setup() will handle the rest.
This is already being done for port 6, do it for port 5 as well.
Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5") Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> --- drivers/net/dsa/mt7530.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 6d33c1050458..3deebdcfeedf 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2203,14 +2203,18 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); + /* Let phylink decide the interface later. If port 5 is used for phy + * muxing, its interface will be handled without involving phylink. + */ + priv->p5_interface = PHY_INTERFACE_MODE_NA; + priv->p6_interface = PHY_INTERFACE_MODE_NA; + /* Enable port 6 */ val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; val |= MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); - priv->p6_interface = PHY_INTERFACE_MODE_NA; - /* Enable and reset MIB counters */ mt7530_mib_reset(ds); -- 2.37.2
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