Messages in this thread | | | Date | Fri, 17 Feb 2023 11:49:51 +0800 | From | kernel test robot <> | Subject | drivers/iommu/io-pgtable-arm.c:330:8: error: instruction requires the following: RV64I Base Instruction Set |
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Hi Lad,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 3ac88fa4605ec98e545fb3ad0154f575fda2de5f commit: 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option date: 3 months ago config: riscv-buildonly-randconfig-r003-20230216 (https://download.01.org/0day-ci/archive/20230217/202302171144.sffQigLX-lkp@intel.com/config) compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project db89896bbbd2251fff457699635acbbedeead27f) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv-linux-gnu # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/iommu/
If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> | Link: https://lore.kernel.org/oe-kbuild-all/202302171144.sffQigLX-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/iommu/io-pgtable-arm.c:330:8: error: instruction requires the following: RV64I Base Instruction Set old = cmpxchg64_relaxed(ptep, curr, new); ^ include/linux/atomic/atomic-instrumented.h:1968:2: note: expanded from macro 'cmpxchg64_relaxed' arch_cmpxchg64_relaxed(__ai_ptr, __VA_ARGS__); \ ^ include/linux/atomic/atomic-arch-fallback.h:60:32: note: expanded from macro 'arch_cmpxchg64_relaxed' #define arch_cmpxchg64_relaxed arch_cmpxchg64 ^ arch/riscv/include/asm/cmpxchg.h:354:2: note: expanded from macro 'arch_cmpxchg64' arch_cmpxchg((ptr), (o), (n)); \ ^ arch/riscv/include/asm/cmpxchg.h:344:23: note: expanded from macro 'arch_cmpxchg' (__typeof__(*(ptr))) __cmpxchg((ptr), \ ^ arch/riscv/include/asm/cmpxchg.h:324:4: note: expanded from macro '__cmpxchg' "0: lr.d %0, %2\n" \ ^ <inline asm>:1:5: note: instantiated into assembly here 0: lr.d s4, 0(s0) ^ >> drivers/iommu/io-pgtable-arm.c:330:8: error: instruction requires the following: RV64I Base Instruction Set old = cmpxchg64_relaxed(ptep, curr, new); ^ include/linux/atomic/atomic-instrumented.h:1968:2: note: expanded from macro 'cmpxchg64_relaxed' arch_cmpxchg64_relaxed(__ai_ptr, __VA_ARGS__); \ ^ include/linux/atomic/atomic-arch-fallback.h:60:32: note: expanded from macro 'arch_cmpxchg64_relaxed' #define arch_cmpxchg64_relaxed arch_cmpxchg64 ^ arch/riscv/include/asm/cmpxchg.h:354:2: note: expanded from macro 'arch_cmpxchg64' arch_cmpxchg((ptr), (o), (n)); \ ^ arch/riscv/include/asm/cmpxchg.h:344:23: note: expanded from macro 'arch_cmpxchg' (__typeof__(*(ptr))) __cmpxchg((ptr), \ ^ arch/riscv/include/asm/cmpxchg.h:326:5: note: expanded from macro '__cmpxchg' " sc.d.rl %1, %z4, %2\n" \ ^ <inline asm>:3:2: note: instantiated into assembly here sc.d.rl a0, s6, 0(s0) ^ 2 errors generated.
Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for IOMMU_IO_PGTABLE_LPAE Depends on [n]: IOMMU_SUPPORT [=y] && (ARM || ARM64 || COMPILE_TEST [=y] && !GENERIC_ATOMIC64 [=y]) Selected by [y]: - IPMMU_VMSA [=y] && IOMMU_SUPPORT [=y] && (ARCH_RENESAS [=y] || COMPILE_TEST [=y] && !GENERIC_ATOMIC64 [=y])
vim +330 drivers/iommu/io-pgtable-arm.c
c896c132b01895 Laurent Pinchart 2014-12-14 310 fb3a95795da53d Robin Murphy 2017-06-22 311 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table, fb3a95795da53d Robin Murphy 2017-06-22 312 arm_lpae_iopte *ptep, 2c3d273eabe8b1 Robin Murphy 2017-06-22 313 arm_lpae_iopte curr, 9abe2ac834851a Hector Martin 2021-11-20 314 struct arm_lpae_io_pgtable *data) fb3a95795da53d Robin Murphy 2017-06-22 315 { 2c3d273eabe8b1 Robin Murphy 2017-06-22 316 arm_lpae_iopte old, new; 9abe2ac834851a Hector Martin 2021-11-20 317 struct io_pgtable_cfg *cfg = &data->iop.cfg; e1d3c0fd701df8 Will Deacon 2014-11-14 318 9abe2ac834851a Hector Martin 2021-11-20 319 new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE; fb3a95795da53d Robin Murphy 2017-06-22 320 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) fb3a95795da53d Robin Murphy 2017-06-22 321 new |= ARM_LPAE_PTE_NSTABLE; e1d3c0fd701df8 Will Deacon 2014-11-14 322 77f3445866c39d Will Deacon 2017-06-23 323 /* 77f3445866c39d Will Deacon 2017-06-23 324 * Ensure the table itself is visible before its PTE can be. 77f3445866c39d Will Deacon 2017-06-23 325 * Whilst we could get away with cmpxchg64_release below, this 77f3445866c39d Will Deacon 2017-06-23 326 * doesn't have any ordering semantics when !CONFIG_SMP. 77f3445866c39d Will Deacon 2017-06-23 327 */ 77f3445866c39d Will Deacon 2017-06-23 328 dma_wmb(); 2c3d273eabe8b1 Robin Murphy 2017-06-22 329 2c3d273eabe8b1 Robin Murphy 2017-06-22 @330 old = cmpxchg64_relaxed(ptep, curr, new); 2c3d273eabe8b1 Robin Murphy 2017-06-22 331 4f41845b340783 Will Deacon 2019-06-25 332 if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC)) 2c3d273eabe8b1 Robin Murphy 2017-06-22 333 return old; 2c3d273eabe8b1 Robin Murphy 2017-06-22 334 2c3d273eabe8b1 Robin Murphy 2017-06-22 335 /* Even if it's not ours, there's no point waiting; just kick it */ 41e1eb2546e9c8 Isaac J. Manjarres 2021-06-16 336 __arm_lpae_sync_pte(ptep, 1, cfg); 2c3d273eabe8b1 Robin Murphy 2017-06-22 337 if (old == curr) 2c3d273eabe8b1 Robin Murphy 2017-06-22 338 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC); 2c3d273eabe8b1 Robin Murphy 2017-06-22 339 2c3d273eabe8b1 Robin Murphy 2017-06-22 340 return old; e1d3c0fd701df8 Will Deacon 2014-11-14 341 } e1d3c0fd701df8 Will Deacon 2014-11-14 342
:::::: The code at line 330 was first introduced by commit :::::: 2c3d273eabe8b1ed3b3cffe2c79643b1bf7e2d4a iommu/io-pgtable-arm: Support lockless operation
:::::: TO: Robin Murphy <robin.murphy@arm.com> :::::: CC: Will Deacon <will.deacon@arm.com>
-- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests
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