Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 17 Feb 2023 10:07:31 +0100 | Subject | Re: drivers/iommu/io-pgtable-arm.c:330:8: error: instruction requires the following: RV64I Base Instruction Set |
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CC linux-riscv
On Fri, Feb 17, 2023 at 4:50 AM kernel test robot <lkp@intel.com> wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master > head: 3ac88fa4605ec98e545fb3ad0154f575fda2de5f > commit: 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > date: 3 months ago > config: riscv-buildonly-randconfig-r003-20230216 (https://download.01.org/0day-ci/archive/20230217/202302171144.sffQigLX-lkp@intel.com/config) > compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project db89896bbbd2251fff457699635acbbedeead27f) > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # install riscv cross compiling tool for clang build > # apt-get install binutils-riscv-linux-gnu > # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 > git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > git fetch --no-tags linus master > git checkout 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv olddefconfig > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/iommu/ > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp@intel.com> > | Link: https://lore.kernel.org/oe-kbuild-all/202302171144.sffQigLX-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > >> drivers/iommu/io-pgtable-arm.c:330:8: error: instruction requires the following: RV64I Base Instruction Set > old = cmpxchg64_relaxed(ptep, curr, new); > ^ > include/linux/atomic/atomic-instrumented.h:1968:2: note: expanded from macro 'cmpxchg64_relaxed' > arch_cmpxchg64_relaxed(__ai_ptr, __VA_ARGS__); \ > ^ > include/linux/atomic/atomic-arch-fallback.h:60:32: note: expanded from macro 'arch_cmpxchg64_relaxed' > #define arch_cmpxchg64_relaxed arch_cmpxchg64 > ^ > arch/riscv/include/asm/cmpxchg.h:354:2: note: expanded from macro 'arch_cmpxchg64' > arch_cmpxchg((ptr), (o), (n)); \ > ^ > arch/riscv/include/asm/cmpxchg.h:344:23: note: expanded from macro 'arch_cmpxchg' > (__typeof__(*(ptr))) __cmpxchg((ptr), \ > ^ > arch/riscv/include/asm/cmpxchg.h:324:4: note: expanded from macro '__cmpxchg' > "0: lr.d %0, %2\n" \ > ^ > <inline asm>:1:5: note: instantiated into assembly here > 0: lr.d s4, 0(s0) > ^
This is a bug in arch/riscv/include/asm/cmpxchg.h, which doesn't cater for the CONFIG_32BIT=y case.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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