Messages in this thread Patch in this message |  | | From | Dario Binacchi <> | Subject | [RFC PATCH v2 09/11] clk: imx: cpu: add device tree support | Date | Sun, 1 Jan 2023 18:57:38 +0100 |
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The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> ---
(no changes since v1)
drivers/clk/imx/clk-cpu.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index cb6ca4cf0535..28fb75c6ecea 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -106,3 +106,57 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, return hw; } EXPORT_SYMBOL_GPL(imx_clk_hw_cpu); + +/** + * of_imx_cpu_clk_setup - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_cpu_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct clk *parent_clk, *div, *mux, *pll, *step; + const char *name = node->name, *parent_name; + + parent_clk = of_clk_get_by_name(node, "fck"); + if (IS_ERR(parent_clk)) { + pr_err("failed to get parent clock for %pOFn\n", node); + return; + } + + div = of_clk_get_by_name(node, "div-clk"); + if (IS_ERR(div)) { + pr_err("failed to get div clock for %pOFn\n", node); + return; + } + + mux = of_clk_get_by_name(node, "mux-clk"); + if (IS_ERR(div)) { + pr_err("failed to get mux clock for %pOFn\n", node); + return; + } + + pll = of_clk_get_by_name(node, "pll-clk"); + if (IS_ERR(div)) { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + step = of_clk_get_by_name(node, "step-clk"); + if (IS_ERR(div)) { + pr_err("failed to get step clock for %pOFn\n", node); + return; + } + + parent_name = __clk_get_name(parent_clk); + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_cpu(name, parent_name, div, mux, pll, step); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, div: %s, mux: %s, pll: %s, step: %s\n", + name, parent_name, __clk_get_name(div), __clk_get_name(mux), + __clk_get_name(pll), __clk_get_name(step)); +} +CLK_OF_DECLARE(fsl_cpu_clk, "fsl,cpu-clock", of_imx_cpu_clk_setup); -- 2.32.0
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