Messages in this thread | | | Subject | Re: [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change | From | Stephen Boyd <> | Date | Wed, 28 Sep 2022 17:18:12 -0700 |
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Quoting Rahul Tanwar (2022-09-21 23:24:28) > One of the clock entry "dcl" clk's rate can only be changed by > changing its parent's clock rate. But it was missing to have > CLK_SET_RATE_PARENT flag as enabled. > > Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to > allow its clk rate to be changed via its parent's clk. > > Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> > ---
Any Fixes tag?
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