Messages in this thread | | | Subject | Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver | From | Stephen Boyd <> | Date | Wed, 28 Sep 2022 17:17:40 -0700 |
| |
Quoting Rahul Tanwar (2022-09-21 23:24:26) > In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled > from EPU (power management IP) in certain power saving modes. If gate > clocks are allowed to be enabled/disabled from CGU clk driver, then > there arises a conflict where in case clk driver disables a gate clk, > and then EPU tries to disable the same gate clk, then it will hang > polling for the clk gated successful status.
Is there any point in registering these clks when they're not supposed to be controlled from Linux?
| |