Messages in this thread | | | Date | Wed, 14 Sep 2022 14:26:20 +0200 | Subject | Re: [PATCH v9,3/7] arm64: dts: mt8192: Add thermal zones and thermal nodes | From | AngeloGioacchino Del Regno <> |
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Il 17/08/22 10:07, bchihi@baylibre.com ha scritto: > From: Balsam CHIHI <bchihi@baylibre.com> > > Add thermal zones and thermal nodes for the mt8192. > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index cbae5a5ee4a0..59ef4da06a70 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -12,6 +12,7 @@ > #include <dt-bindings/pinctrl/mt8192-pinfunc.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/power/mt8192-power.h> > +#include <dt-bindings/reset/mt8192-resets.h> > > / { > compatible = "mediatek,mt8192"; > @@ -599,6 +600,28 @@ spi0: spi@1100a000 { > status = "disabled"; > }; > > + lvts_ap: thermal-sensor@1100b000 { > + compatible = "mediatek,mt8192-lvts-ap"; > + #thermal-sensor-cells = <1>; > + reg = <0 0x1100b000 0 0x1000>; > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_THERM>; > + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; > + nvmem-cells = <&lvts_e_data1>; > + nvmem-cell-names = "lvts_calib_data1"; > + }; > + > + lvts_mcu: thermal-sensor@11278000 {
Please keep the nodes ordered by reg start.
Regards, Angelo
> + compatible = "mediatek,mt8192-lvts-mcu"; > + #thermal-sensor-cells = <1>; > + reg = <0 0x11278000 0 0x1000>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_THERM>; > + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; > + nvmem-cells = <&lvts_e_data1>; > + nvmem-cell-names = "lvts_calib_data1"; > + }; > + > spi1: spi@11010000 { > compatible = "mediatek,mt8192-spi", > "mediatek,mt6765-spi";
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