Messages in this thread | | | Date | Wed, 29 Jun 2022 19:47:08 +0100 | From | Sudeep Holla <> | Subject | Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo |
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On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote: > On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > On 27/06/2022 17:50, Sudeep Holla wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >> > >> The cacheinfo is now initialised early along with the CPU topology > >> initialisation. Instead of relying on the LLC ID information parsed > >> separately only with ACPI PPTT elsewhere, migrate to use the similar > >> information from the cacheinfo. > >> > >> This is generic for both DT and ACPI systems. The ACPI LLC ID information > >> parsed separately can now be removed from arch specific code. > > > > Hey Sudeep, > > I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/ > > I suspect the issue is a missing "next-level-cache" in the the dt: > > arch/riscv/boot/dts/microchip/mpfs.dtsi
Good that I included this in -next, I had not received any feedback from RISC-V even after 5 iterations. I also see this DTS is very odd. It also states CPU0 doesn't have L1-D$ while the other 4 CPUs have L1-D$. Is that a mistake or is it the reality ? Another breakage in userspace cacheinfo sysfs entry of cpu0 has both I$ and D$.
-- Regards, Sudeep
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