Messages in this thread | | | From | Samuel Holland <> | Subject | [PATCH 0/5] genirq/irqchip: RISC-V PLIC cleanup and optimization | Date | Sun, 8 May 2022 22:43:28 -0500 |
| |
This series removes the splinlocks and cpumask operations from the PLIC driver's hot path. To do that, it first makes the IRQ affinity mask behavior more consistent between uniprocessor and SMP configurations. (The Allwinner D1 is a uniprocessor SoC containing a PLIC.)
A further optimization is to take advantage of the fact that multiple IRQs can be claimed at once. This allows removing the mask operations for oneshot IRQs -- i.e. the combination of IRQCHIP_ONESHOT_SAFE and IRQCHIP_EOI_THREADED, which is not currently supported. I will send this as a separate series, since it makes more invasive changes to the generic IRQ code.
Samuel Holland (5): genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP genirq: Refactor accessors to use irq_data_get_affinity_mask genirq: Provide an IRQ affinity mask in non-SMP configs irqchip/sifive-plic: Make better use of the effective affinity mask irqchip/sifive-plic: Separate the enable and mask operations
arch/arm/mach-hisi/Kconfig | 2 +- drivers/irqchip/Kconfig | 15 ++++---- drivers/irqchip/irq-sifive-plic.c | 61 ++++++++++++++++--------------- include/linux/irq.h | 20 ++++++---- kernel/irq/Kconfig | 1 + 5 files changed, 54 insertions(+), 45 deletions(-)
-- 2.35.1
| |