| Date | Tue, 22 Feb 2022 15:13:46 +0100 | From | Michael Walle <> | Subject | Re: [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode |
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Am 2022-02-22 14:54, schrieb Tudor.Ambarus@microchip.com: > On 2/21/22 09:44, Michael Walle wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the content is safe >> >> Am 2022-02-18 15:58, schrieb Tudor Ambarus: >>> Fortunately there are controllers >>> that can swap back the bytes at runtime, fixing the endiannesses. >>> Provide >>> a way for the upper layers to specify the byte order in DTR mode. >> >> Are there any patches for the atmel-quadspi yet? What happens if > > not public, but will publish them these days. > >> the controller doesn't support it? Will there be a software fallback? > > no need for a fallback, the controller can ignore op->data.dtr_bswap16 > if > it can't swap bytes.
I don't understand. If the controller doesn't swap the 16bit values, you will read the wrong content, no?
-michael
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