Messages in this thread | | | Date | Wed, 28 Dec 2022 12:37:30 +0100 | Subject | Re: [PATCH 1/2] arm64: dts: qcom: sm8350: add missing core_bi_pll_test_se GCC clock | From | Konrad Dybcio <> |
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On 28.12.2022 12:24, Krzysztof Kozlowski wrote: > The GCC bindings expect core_bi_pll_test_se clock input, even if it is > optional: > > sm8350-mtp.dtb: clock-controller@100000: clock-names:2: 'core_bi_pll_test_se' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Is it even going to be used by anybody, or should we just drop it on the driver side as per usual?
Konrad > arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index d473194c968d..d5747bb467e0 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -644,6 +644,7 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > clock-names = "bi_tcxo", > "sleep_clk", > + "core_bi_pll_test_se", > "pcie_0_pipe_clk", > "pcie_1_pipe_clk", > "ufs_card_rx_symbol_0_clk", > @@ -661,6 +662,7 @@ gcc: clock-controller@100000 { > <0>, > <0>, > <0>, > + <0>, > <&ufs_phy_rx_symbol_0_clk>, > <&ufs_phy_rx_symbol_1_clk>, > <&ufs_phy_tx_symbol_0_clk>,
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