| Date | Fri, 28 Oct 2022 17:43:21 +0530 | From | Vinod Koul <> | Subject | Re: [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration |
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On 14-10-22, 00:08, Vidya Sagar wrote: > Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change > to Gen1 during initialization. This helps in the below surprise link down > cases, > - Surprise link down happens at Gen3/Gen4 link speed. > - Surprise link down happens and external REFCLK is cut off, which causes > UPHY PLL rate to deviate to an invalid rate.
Applied, thanks
-- ~Vinod
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