Messages in this thread | | | Date | Mon, 17 Oct 2022 18:54:48 +0800 | From | Huang Rui <> | Subject | Re: [RESEND PATCH V2 6/9] cpufreq: amd_pstate: add AMD pstate EPP support for shared memory type processor |
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On Tue, Oct 11, 2022 at 12:22:45AM +0800, Yuan, Perry wrote: > Add Energy Performance Preference support for AMD SOCs which do not > contain a designated MSR for CPPC support. A shared memory interface > is used for CPPC on these SOCs and the ACPI PCC channel is used to > enable EPP and reset the desired performance. > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > --- > drivers/cpufreq/amd-pstate.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 2d28f458589c..08f9e335f97c 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -135,12 +135,25 @@ static inline int pstate_enable(bool enable) > > static int cppc_enable(bool enable) > { > + struct cppc_perf_ctrls perf_ctrls; > int cpu, ret = 0; > > for_each_present_cpu(cpu) { > ret = cppc_set_enable(cpu, enable); > if (ret) > return ret; > + if (epp) { > + /* Enable autonomous mode for EPP */ > + ret = cppc_set_auto_epp(cpu, enable); > + if (ret) > + return ret; > + > + /* Set desired perf as zero to allow EPP firmware control */ > + perf_ctrls.desired_perf = 0; > + ret = cppc_set_perf(cpu, &perf_ctrls); > + if (ret) > + return ret; > + }
This patch only writes the desired_perf as 0 to enable the EPP function, but it cannot be an independent function or patch without the dependency of the next one (patch 7).
Thanks, Ray
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