lkml.org 
[lkml]   [2021]   [Aug]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
SubjectRe: [PATCH 09/10] arm64: Enable workaround for TRBE overwrite in FILL mode
From
Date


On 7/28/21 7:22 PM, Suzuki K Poulose wrote:
> Now that we have the work around implmented in the TRBE

Typo ^^^^^

> driver, add the Kconfig entries and document the errata.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index d410a47ffa57..2f99229d993c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -92,12 +92,16 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
> +----------------+-----------------+-----------------+-----------------------------+
> +| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
> ++----------------+-----------------+-----------------+-----------------------------+
> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM | Neoverse-N1 | #1349291 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
> +----------------+-----------------+-----------------+-----------------------------+
> +| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
> ++----------------+-----------------+-----------------+-----------------------------+
> | ARM | MMU-500 | #841119,826419 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> +----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index b5b13a932561..ad301045dafc 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -669,6 +669,45 @@ config ARM64_ERRATUM_1508412
>
> If unsure, say Y.
>
> +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> + bool

Should this be moved to the earlier patch (7/10) which detects the erratum ?
Might be better to add the definition in Kconfig (even though not selected)
when using it for the first time.

> +
> +config ARM64_ERRATUM_2119858
> + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
> + default y
> + depends on CORESIGHT_TRBE
> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> + help
> + This option adds the workaround for ARM Cortex-A710 erratum 2119858.
> +
> + Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace
> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in

Typo ^^^^^^

> + the event of a WRAP event.
> +
> + Work around the issue by always making sure we move the TRBPTR_EL1 by
> + 256bytes before enabling the buffer and filling the first 256bytes of

Nit: space ^^ space ^^

> + the buffer with ETM ignore packets upon disabling.
> +
> + If unsure, say Y.
> +
> +config ARM64_ERRATUM_2139208
> + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
> + default y
> + depends on CORESIGHT_TRBE
> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> + help
> + This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
> +
> + Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace
> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in
Typo ^^^^^^
> + the event of a WRAP event.
> +
> + Work around the issue by always making sure we move the TRBPTR_EL1 by
> + 256bytes before enabling the buffer and filling the first 256bytes of

Nit: space ^^ space ^^

> + the buffer with ETM ignore packets upon disabling.
> +
> + If unsure, say Y.
> +
> config CAVIUM_ERRATUM_22375
> bool "Cavium erratum 22375, 24313"
> default y
>

Otherwise LGTM.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

\
 
 \ /
  Last update: 2021-08-02 11:35    [W:0.262 / U:0.456 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site