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    SubjectRe: [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode
    Hi Suzuki,

    On Wed, Jul 28, 2021 at 7:23 PM Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
    >
    > Arm Neoverse-N2 and the Cortex-A710 cores are affected
    > by a CPU erratum where the TRBE will overwrite the trace buffer
    > in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
    > when it reaches the limit and wraps to the base to continue
    > writing upto 3 cache lines. This will overwrite any trace that
    > was written previously.
    >
    > Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum
    > (#2119858) to the detection logic.
    >
    > This will be used by the TRBE driver in later patches to work
    > around the issue. The detection has been kept with the core
    > arm64 errata framework list to make sure :
    > - We don't duplicate the framework in TRBE driver
    > - The errata detection is advertised like the rest
    > of the CPU errata.
    >
    > Note that the Kconfig entries will be added after we have added
    > the work around in the TRBE driver, which depends on the cpucap
    > from here.
    >
    > Cc: Will Deacon <will@kernel.org>
    > Cc: Mark Rutland <mark.rutland@arm.com>
    > Cc: Anshuman Khandual <anshuman.khandual@arm.com>
    > Cc: Catalin Marinas <catalin.marinas@arm.com>
    > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
    > Cc: Mike Leach <mike.leach@linaro.org>
    > cc: Leo Yan <leo.yan@linaro.org>
    > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    > ---
    > arch/arm64/kernel/cpu_errata.c | 25 +++++++++++++++++++++++++
    > arch/arm64/tools/cpucaps | 1 +
    > 2 files changed, 26 insertions(+)
    >
    > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
    > index e2c20c036442..ccd757373f36 100644
    > --- a/arch/arm64/kernel/cpu_errata.c
    > +++ b/arch/arm64/kernel/cpu_errata.c
    > @@ -340,6 +340,18 @@ static const struct midr_range erratum_1463225[] = {
    > };
    > #endif
    >
    > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
    > +static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
    > +#ifdef CONFIG_ARM64_ERRATUM_2139208
    > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
    > +#endif
    > +#ifdef CONFIG_ARM64_ERRATUM_2119858
    > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
    > +#endif
    > + {},
    > +};
    > +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
    > +
    > const struct arm64_cpu_capabilities arm64_errata[] = {
    > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
    > {
    > @@ -533,6 +545,19 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
    > .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
    > ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
    > },
    > +#endif
    > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
    > + {
    > + /*
    > + * The erratum work around is handled within the TRBE
    > + * driver and can be applied per-cpu. So, we can allow
    > + * a late CPU to come online with this erratum.
    > + */
    > + .desc = "ARM erratum 2119858 or 2139208",
    > + .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
    > + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
    > + CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
    > + },
    > #endif
    > {
    > }
    > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
    > index 49305c2e6dfd..1ccb92165bd8 100644
    > --- a/arch/arm64/tools/cpucaps
    > +++ b/arch/arm64/tools/cpucaps
    > @@ -53,6 +53,7 @@ WORKAROUND_1418040
    > WORKAROUND_1463225
    > WORKAROUND_1508412
    > WORKAROUND_1542419
    > +WORKAROUND_TRBE_OVERWRITE_FILL_MODE
    > WORKAROUND_CAVIUM_23154
    > WORKAROUND_CAVIUM_27456
    > WORKAROUND_CAVIUM_30115

    We need to keep this list sorted ?

    > --
    > 2.24.1
    >
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    > CoreSight mailing list
    > CoreSight@lists.linaro.org
    > https://lists.linaro.org/mailman/listinfo/coresight

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