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SubjectRe: [PATCH v2] ARM: dts: stm32: add a new DCMI pins group
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Hi

On 6/3/21 5:34 PM, Grzegorz Szymaszek wrote:
> The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
> stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI
> interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was
> incompatible with the pins used on the Odyssey board, where:
> - there are 8 data pins instead of 12,
> - DCMI_HSYNC is available at PA4 instead of PH8,
> - DCMI_D0 is at PC6 instead of PH9,
> - DCMI_D3 is at PE1 instead of PH12,
> - DCMI_D4 is at PE11 instead of PH14,
> - DCMI_D5 is at PD3 instead of PI4,
> - DCMI_D6 is at PE13 instead of PB8,
> - DCMI_D7 is at PB9 instead of PE6.
>
> Add the DCMI pins used on the Odyssey board as a new DCMI pin state
> definition, dcmi-1, AKA phandle dcmi_pins_b.
>
> Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
> ---
> V1 -> V2: Removed the pinctrl override from the Odyssey device tree,
> added a new pinctrl in stm32mp15-pinctrl.dtsi instead
>
> arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>

Applied on stm32-next. I just updated the commit title by
"ARM: dts: stm32: add a new DCMI pins group on stm32mp15"

Thanks.
Alex


> diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> index 060baa8b7e9d..5b60ecbd718f 100644
> --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> @@ -118,6 +118,39 @@ pins {
> };
> };
>
> + dcmi_pins_b: dcmi-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
> + bias-disable;
> + };
> + };
> +
> + dcmi_sleep_pins_b: dcmi-sleep-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
> + };
> + };
> +
> ethernet0_rgmii_pins_a: rgmii-0 {
> pins1 {
> pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
>

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