Messages in this thread | | | Date | Thu, 27 May 2021 13:21:38 +0100 | From | Marc Zyngier <> | Subject | Re: [RFC PATCH v2 09/10] irqchip/gic: Convert to handle_strict_flow_irq() |
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On Tue, 25 May 2021 18:32:54 +0100, Valentin Schneider <valentin.schneider@arm.com> wrote: > > Now that the proper infrastructure is in place, convert the irq-gic chip to > use handle_strict_flow_irq() along with IRQCHIP_AUTOMASKS_FLOW. > > For EOImode=1, the Priority Drop is moved from gic_handle_irq() into > chip->irq_ack(). This effectively pushes the EOI write down into > ->handle_irq(), but doesn't change its ordering wrt the irqaction > handling. > > The EOImode=1 irqchip also gains IRQCHIP_EOI_THREADED, which allows the > ->irq_eoi() call to be deferred to the tail of ONESHOT IRQ threads. This > means a threaded ONESHOT IRQ can now be handled entirely without a single > chip->irq_mask() call. > > EOImode=0 handling remains unchanged. > > Signed-off-by: Valentin Schneider <valentin.schneider@arm.com> > --- > drivers/irqchip/irq-gic.c | 14 +++++++++++--- > 1 file changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index b1d9c22caf2e..4919478c3e41 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -344,8 +344,6 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) > if (unlikely(irqnr >= 1020)) > break; > > - if (static_branch_likely(&supports_deactivate_key)) > - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); > isb(); > > /* > @@ -1012,7 +1010,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, > break; > default: > irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, > - handle_fasteoi_irq, NULL, NULL); > + static_branch_likely(&supports_deactivate_key) ? > + handle_strict_flow_irq : handle_fasteoi_irq, > + NULL, NULL); > irq_set_probe(irq); > irqd_set_single_target(irqd); > break; > @@ -1116,8 +1116,16 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, > > if (use_eoimode1) { > gic->chip.irq_mask = gic_eoimode1_mask_irq; > + gic->chip.irq_ack = gic_eoi_irq; > gic->chip.irq_eoi = gic_eoimode1_eoi_irq; > gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; > + > + /* > + * eoimode0 shouldn't expose FLOW_MASK because the priority > + * drop is undissociable from the deactivation, and we do need > + * the priority drop to happen within the flow handler. > + */ > + gic->chip.flags |= IRQCHIP_AUTOMASKS_FLOW | IRQCHIP_EOI_THREADED; > } > > if (gic == &gic_data[0]) {
How about GICv2M, GICv3-MBI, and the collection of widget that build a domain on top of a GIC domain? I'm worried that they now all need updating one way or another...
M.
-- Without deviation from the norm, progress is not possible.
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