Messages in this thread Patch in this message | | | From | , | Subject | [PATCH v1] clk: rockchip: Optimize PLL table memory usage | Date | Tue, 11 May 2021 17:07:26 +0800 |
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From: Elaine Zhang <zhangqing@rock-chips.com>
Before the change: The sizeof rk3568_pll_rates = 2544 Use union: The sizeof rk3568_pll_rates = 1696
In future Soc, more PLL types will be added, and the rockchip_pll_rate_table will add more members, and the space savings will be even more pronounced by using union.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk.h | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 571cee7bbfdc..7aa45cc70287 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -271,17 +271,24 @@ struct rockchip_clk_provider { struct rockchip_pll_rate_table { unsigned long rate; - unsigned int nr; - unsigned int nf; - unsigned int no; - unsigned int nb; - /* for RK3036/RK3399 */ - unsigned int fbdiv; - unsigned int postdiv1; - unsigned int refdiv; - unsigned int postdiv2; - unsigned int dsmpd; - unsigned int frac; + union { + struct { + /* for RK3066 */ + unsigned int nr; + unsigned int nf; + unsigned int no; + unsigned int nb; + }; + struct { + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; + }; + }; }; /** -- 2.17.1
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