Messages in this thread | | | Subject | Re: [PATCH net-next v1 3/9] net: dsa: qca: ar9331: reorder MDIO write sequence | From | Florian Fainelli <> | Date | Sat, 3 Apr 2021 19:17:43 -0700 |
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On 4/3/2021 04:48, Oleksij Rempel wrote: > In case of this switch we work with 32bit registers on top of 16bit > bus. Some registers (for example access to forwarding database) have > trigger bit on the first 16bit half of request and the result + > configuration of request in the second half. Without this this patch, we would > trigger database operation and overwrite result in one run. > > To make it work properly, we should do the second part of transfer > before the first one is done. > > So far, this rule seems to work for all registers on this switch. > > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Seems like you could send this as a separate bugfix for the "net" tree along with a Fixes tag? -- Florian
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